Memory devices, such as nonvolatile memory devices, can use single ended current sensing schemes. One example of a single ended current sensing scheme is shown in FIG. 7 and designated by the general reference character 700. A single ended current sensing arrangement 700 can include a number of memory cells (e.g., 702) each connected to a bit line (BLn, BL(n+1)) and a word line (WL0 to WLm). When a memory cell (e.g., 702) is selected, it can create a current path to draw a current Icell. A memory cell current (Icell) can vary according to a data value stored. Sense amplifiers (SAn, SA(n+1)) can be connected to groups of cells, such as columns or groups of columns. Each sense amplifier (SAn, SA(n+1)) can compare a cell current (Icell) to a reference value to determine the value of the data stored in the selected cell (e.g., 0 or 1). For example, for some technologies, a programmed memory cell can draw less current than an erased (or nonprogrammed memory cell).
To provide current sensing memory devices with fast access speeds, it is desirable for a current sense amplifier to amplify sensed current differences into an output voltage in as short a period of time as possible.
To better understand various aspects of the disclosed embodiments, a conventional current sense amplifier will now be described with reference to FIG. 6.
FIG. 6 shows a conventional sense amplifier (SA) 600 that has a precharge (equalization) mode of operation and a sense mode of operation.
In a precharge mode, equalization signal saeq can be active (in this case high), while a sense enable signal saenb can be inactive (in this case high). With signal saenb high, an enable p-channel metal-oxide semiconductor (PMOS) transistor P60 can be turned off. With signal saeq high, precharge PMOS transistors P62 and P64 can be turned on, pulling first data node 602 and second data node 604 to a high power supply voltage VCC. In alternate conventional arrangements, diode connected p-channel devices can be included in such precharge paths, and first data and second data nodes (602 and 604) can be precharged to VCC−Vtp, where Vtp is a threshold voltage of such diode connected transistors. In addition, signal saeq can turn on complementary MOS (CMOS) passgate T60, to ensure first and second data nodes (602 and 604) are at same precharge potential (i.e., equalized).
In a sense mode, equalization signal saeq can be inactive (in this case low), while a sense enable signal saenb can be active (in this case low). With signal saeq low, precharge transistors (P62 and P64), and passgate T60 can be off, isolating first and second data nodes (602 and 604) from one another. At the same time, with signal saenb low, enable transistor P60 can be turned on, coupling a load circuit 606 to a high power supply voltage VCC. Load circuit 606 can complete a path for a current Icell between a selected memory cell and VCC, as well as a path for current Iref between a low power supply VSS and VCC.
In some conventional arrangements, a load circuit 606 can include a first resistor between a first data node 602 and PMOS device 60, and a second resistor between a second data node 604 and PMOS device 60. In an alternate conventional arrangement, a load device can include two transistors connected in a current mirror configuration.
As shown in FIG. 6, the generation of a reference current Iref can be established by a bias voltage NBIAS applied to the gate of transistor N64. Ideally, a reference current Iref can be set to have a value between a current drawn by an erased memory cell, and that drawn by a programmed memory cell.
In a sense operation, at the same time a current Iref is being drawn through second data node 604, a current Icell can be drawn through first data node 602 in response to a selected memory cell. If Icell>Iref, then first data node 602 can be pulled to a lower potential than second data node 604, creating a differential voltage representing one type of stored data value. Conversely, if Icell<Iref, then second data node 604 can be pulled to a lower voltage than first data node 602. Such a difference in potential at first and second data nodes (602 and 604) can be further amplified by one or more downstream voltage amplifiers to generate an output read data value.
Conventional SA 600 can also include current/voltage limit NMOS devices N60 and N62 which can limit a maximum value for currents Icell and Iref; or limit a maximum value for voltage on the memory cell bitline. In particular, a limit voltage Vlim can be applied to the gates of such devices.
A drawback to an arrangement like that of FIG. 6 can be that the use of resistors within a load circuit 606, whether implemented as polycrystalline (polysilicon) resistors or substrate diffusion regions, can require considerable substrate area in the event currents Icell and Iref are small.
In addition, if data nodes (602 and 604) are pre-charged to VCC, such data nodes can take substantial amounts of time to reach a final value suitable for sensing because the common mode of the output differential voltage is usually set close to VCC/2 for the subsequent amplifier stages to amplify quickly.
At the same time, precharging data nodes (602 and 604) to a value VCC−Vtp using diode connected PMOS devices can be impractical at low voltage applications as such a Vtp drop from VCC can create “headroom” issues for the sense amplifier and for the memory cell. That is, the working range of voltages for sensing operations can be undesirable small.
Yet another problem that can arise from a conventional approach like that of FIG. 6 can be that some nonvolatile memory technologies have cell current values that can change with temperature and/or due to aging of the memory cells. To accommodate such changes, a reference current should move correspondingly. However, when a reference current Iref moves up or down significantly (around +/−50%), then a common mode operating point of the output differential can move significantly, as a load circuit 606 can continue to provide a same load value.